Electronic components are subject to operating characteristic variations. Although devices may be manufactured according to specification, no manufacturing technique can guarantee uniformity across all devices. In metal oxide semiconductor (MOS) devices, this variation is often manifested as a shifting of a threshold voltage level. For example, in a comparator circuit, mismatches in the differential pair and mismatches in the current sources may result in a comparator offset, which is a voltage offset that limits the accuracy of the comparator by affecting the performance of a comparison between an input voltage and a reference voltage. Comparator offsets occur not only as a result of random device mismatches, but are also a function of device size. One known method of reducing offsets is to increase device size. However, this requires increased power to maintain gain-bandwidth and regeneration time. For small, low-power comparators, increasing device size may not be a practical option, so that an offset compensation or cancellation scheme is required.
Comparator offsets may be categorized into two types. A first type, known as DC offset (also referred to herein as a “static” offset) is a more or less constant offset that exists when the comparator circuit is operational. A second type, referred to herein as a “dynamic” offset, occurs when the comparator circuit is switched to output a comparator decision based on the values of the inputs to the circuit. Dynamic offsets may be caused by imbalances in the circuit, such as parasitic capacitances that affect circuit components. Therefore, the causes of dynamic offsets may be unrelated to the causes of static offsets.
Techniques exist to compensate for static offsets. However, dynamic offsets remain a problem.